Because of their inherent flexibility and the ability to readily re-configure PLDs, PLDs have increasingly proliferated in many areas of technology, such as data processing and signal processing applications. PLDs may include not only the conventional PLD fabric (programmable logic), but also relatively sophisticated blocks of circuitry, or intellectual property (IP).
The addition of the IP blocks increases the utility and power of PLDs. Nevertheless, IP blocks, such as processors, often use particular communication methodology, such as a particular bus communication protocol. Although a particular bus may facilitate communication with a given IP block, it may also hinder data throughput in the PLD. Put another way, the PLD's adherence to the bus communication protocol, while providing for communication with the IP block(s), may nevertheless adversely impact the data throughput and, hence, the overall performance, of the PLD. A need therefore exists for accommodating desired buses and their respective communication protocols without necessarily hindering the performance of the PLD.